The present invention relates generally to data processing systems and is specifically directed to a data processing system having a central processing unit (CPU), a video memory array and a controller for controlling the operation of a video display unit such as a cathode ray tube (CRT) as used in word processing.
The general organization of a data processing system including a video display unit for the presentation of information thereon includes a microprocessor, a memory unit, a video display controller and a bus system comprising control, address and data buses which interconnect the various elements of the system. Where the data processing system includes a cathode ray tube, the video display controller is referred to as a CRT controller which is adapted to sequentially access the memory unit for display instructions that direct what graphics are to be generated and how the graphics are to be displayed. Under the direction of these display instructions, the CRT controller executes additional memory unit accesses to obtain stored graphics information that is converted to video information of predetermined characteristics. The memory unit, which is generally referred to as the video memory array, is a random access memory (RAM) device in which digital data is stored which is red therefrom synchronously with the raster scanning of the picture elements on the face of the CRT. The CPU is responsive to user initiated inputs and is generally comprised of a microprocessor used to update or modify the digital data stored in the video memory array and hence modify the picture displayed on the CRT's screen.
In controlling those locations in the video memory array from which graphics information is read by the CRT controller and provided to the video display unit, the CPU writes information into the video memory array. In response to this information, the CRT controller provides predetermined address locations to video logic circuitry in the system for displaying the desired information. Thus, in early data processing systems, CPU operation was limited to writing information into the video memory array while CRT controller operation was limited to reading information from the video memory array.
Another, later approach for interfacing the various components of a data processing system has the CPU directly coupled only to the CRT controller. In this scheme, the CPU provides various commands to the CRT controller which, in turn, selectively accesses the video memory array in writing instructions therein and reading the appropriate digital data therefrom in generating CRT display commands. This approach requires a relatively sophisticated CRT controller capable of simultaneously processing CPU input commands and video RAM array control signals for driving the CRT.
Still another approach, gaining increasing acceptance, is known as "dual porting" wherein both the CPU and the CRT controller have access to the video RAM array with the CRT controller capable of only reading data from the video RAM array while the CPU is capable of either reading from or writing to the video RAM array. The CPU writes information to the video RAM array for accessing various of the plurality of addressable memory locations therein. The CPU may also be required to read data from the video RAM array in order to perform a specific function. For example, if the user desires to remove only a portion of the graphics display from the CRT's screen, the CPU will read the data stored in the video RAM array and provide appropriate erase commands to the video RAM array for removing selected portions of the video graphics display.
The "dual porting" approach, while affording enhanced system capabilities, places increased performance requirements upon the various components of the data processing system. For example, because of this selective accessing technique, the video RAM array must be capable of high speed read and write operations. In addition, since for the majority of time the CRT controller is accessing the video RAM array in providing a continuous display of information on the CRT's screen, the CPU must be capable of high speed accessing of the video RAM array for extremely short periods so as to avoid degradation of video display quality. Higher speed components generally drive up the cost and complexity of the data processing system. The goal, of course, is to resolve the video RAM array accessing contention between the CPU and the CRT controller using existing components, if possible, or in minimizing system cost and complexity in designing new systems.
One approach to resolving the contention between the CPU and the CRT controller in accessing the video RAM array is disclosed in reissued U.S. Pat. No. Re. 30,785 to Lovercheck, et al., wherein is described a microcomputer terminal system having a first set of shift registers receiving character data from a memory for the input/output devices and a second set of shift registers receiving character data from the first set of shift registers for providing this character data to a character generator for displaying data on the screen of a CRT. When the second set of shift registers advances character data to the CRT, the first set of shift registers receives the character data to be displayed in the succeeding row on the CRT. The first set of shift registers can thus delay loading of the character data from the memory to the first set of shift registers in providing access priority to the system's microprocessor. Thus, the microprocessor can operate at its own rate and obtain priority over the use of the system bus without interrupting the screen refresh cycle or the CRT display.
Another approach is described in U.S. Pat. No. 4,298,931 to Tachiuchi, et al., wherein a plurality of character store RAMs are accessible by a CPU and display timing signal generation means for the simultaneous access and operation of these RAMs. During one character display time a first character store RAM is subjected to a read/write operation by the CPU. At this time, a second character store RAM is subjected to a read operation by a display timing signal from the display timing signal means and a third character store RAM is refreshed. These concurrent operations of the three RAMs are sequentially switched for each character display time permitting the CRT to display characters at all times.
The present invention is intended to provide for the high speed accessing of the video RAM array by the system's CPU while still affording extended periods of video data transfer from the video RAM array to the system's video display in accordance with instructions provided to a video display controller. Thus, high quality graphics is available without the need for multiple RAM arrays, high speed and expensive components and complicated data shifting schemes.